Digital Design Verification Engineer

About the role

We are looking for a driven Digital Design Verification Engineer to join our semiconductor design hub in Valencia, Spain. You will play a critical part in verifying complex mixed‑signal integrated circuits and advanced system‑on‑chip (SoC) architectures, collaborating with multidisciplinary teams from concept through tape‑out.

Key responsibilities

• Develop and maintain SystemVerilog/UVM testbench architectures for ASIC and FPGA designs.
• Create verification plans, generate constrained‑random test scenarios and drive functional and code coverage closure.
• Perform mixed‑signal verification of processor‑based SoCs and ensure design quality up to tape‑out.
• Automate verification flows using scripting languages and standard EDA simulation tools.
• Collaborate with design, architecture and verification teams to resolve issues and improve methodologies.

Required profile

• Hands‑on professional experience in ASIC/FPGA digital design verification, especially for complex mixed‑signal or processor‑based SoCs.
• Strong problem‑solving abilities and effective communication skills in English.

Required skills

• SystemVerilog
• UVM
• Python, Perl or TCL scripting
• Verification‑plan generation and constrained‑random verification
• Functional and code coverage analysis
• Standard EDA simulation tools