DMS Verification Engineer

About the role

We are looking for an experienced DMS (Directed Mixed‑Signal) Verification Engineer to join our engineering team in Valencia. You will work closely with system architects and analog/digital designers to create and execute verification strategies for cutting‑edge mixed‑signal SoCs.

Key responsibilities

• Drive specification reviews and generate initial verification plans using Vmanager.
• Define verification strategies, balancing DMS and DV, and model versus schematic equivalence.
• Plan resources, schedules and track progress, identifying potential show‑stoppers.
• Implement verification plans, run regressions and monitor functional and code coverage.
• Validate behavioral models against circuit‑level simulations and measurements.
• Perform root‑cause analysis and debug issues down to RTL, gate and schematic levels.
• Maintain and improve verification infrastructure, flows and UVM methodology.
• Provide technical leadership and mentorship across multi‑site engineering teams.

Required profile

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Telecommunications, Computer Science or related field.
• Proven experience developing validation plans, analysing test results and debugging failures at RTL, gate and schematic levels.
• Strong working knowledge of SystemVerilog/Verilog and UVM.
• Experience with gate‑level simulations (GLS) and DSP techniques.
• Professional proficiency in English (minimum C1) and valid EU work authorization.

Required skills

• SystemVerilog
• Verilog
• UVM methodology
• Gate‑Level Simulation (GLS)
• DSP techniques
• Analog schematic analysis
• Python scripting
• Make
• Shell scripting