Senior Layout & Design Automation Engineer

About the role

Analog Devices' Platform IP organization is looking for an experienced Senior Layout & Design Automation Engineer. The role combines deep expertise in analog and mixed-signal IC layout with a focus on engineering productivity, automation and IP reuse. You will deliver complex block and subsystem layouts while improving layout methodologies, automation frameworks and reusable IP infrastructure, working with circuit designers, layout engineers, EE teams and technology experts.

Key responsibilities

• Lead development of complex analog and mixed-signal layouts from floorplanning through tapeout, owning layout execution for critical IP, subsystems and test chips.
• Drive high-quality layouts for data converters, power management circuits, amplifiers, PLLs and high-voltage designs, meeting performance, matching, reliability, ESD, latch-up and manufacturability requirements.
• Drive DRC, LVS, ERC, EMIR and parasitic extraction closure.
• Develop and deploy automation solutions, identify repetitive tasks and support automated layout generation, layout verification, IP qualification workflows, reusable analog building blocks and AI-assisted design.
• Partner with CAD and EDA teams to improve design flows and tool integration.
• Contribute to reusable Platform IP across technology nodes, support IP migration and reuse, and promote containerized IP, version control and design traceability.
• Mentor layout engineers, perform layout reviews and design audits, and contribute to engineering standards and training materials.

Required profile

• BS, MS or equivalent in Electrical or Electronics Engineering or a related discipline.
• 8+ years of analog or mixed-signal IC layout experience.
• Proven experience delivering silicon in advanced and mature process technologies.
• Preferred: experience developing engineering automation used by multiple users, analog layout generators and parameterized cells, AI-assisted workflows, IP libraries shared across design groups, multiple foundries and process nodes, distributed global teams, and prior technical leadership.

Required skills

• Cadence Virtuoso
• Layout XL / VXL methodologies
• Calibre DRC, LVS, ERC and extraction flows
• Device matching, parasitics, shielding and isolation, reliability and ESD, power distribution and substrate management
• Scripting and automation with Python, Shell/Bash or Tcl