Staff Hardware Security I/O Engineer

About the role

Join the Security I/O Hardware Design team to lead the design, development, and integration of advanced I/O and security IPs for high‑performance SoCs. You will own complex IP projects, work with both proprietary and third‑party technologies, and ensure hardware integrity and confidentiality.

Key responsibilities

• Drive design, development, and integration of advanced high‑speed (UCIe, PCIe, CXL, LPDDR) and low‑speed (APB, I2C, I3C, UART) I/O solutions.
• Lead implementation of security features across the SoC, including secure boot, cryptographic modules (AES, RSA, PUF, RNG) and Trusted Computing Base concepts.
• Design hardware subsystems such as processing units, interconnects, memory, accelerators, and analog components.
• Collaborate with system, architecture, software, digital design and verification teams to ensure cross‑functional convergence.
• Evaluate, integrate, and validate hard and soft security and I/O IPs, managing dependencies and issue resolution.

Required profile

• Bachelor’s, Master’s or PhD in Electrical or Computer Engineering.
• 10+ years of experience in IP/SoC architecture and design for ASIC or FPGA.
• Proven ability to lead complex IP projects and work across multidisciplinary teams.

Required skills

• Deep knowledge of Processor Microcontroller Subsystem (RISC‑V core), secure boot and power management.
• Expertise in high‑speed I/O interfaces: UCIe, PCIe, CXL, LPDDR.
• Proficiency in low‑speed I/O: APB, I2C, I3C, UART.
• Experience with data management, DMA, and NoC architectures (AMBA, AXI, CHI).
• Strong background in hardware security: AES, RSA, PUF, RNG, isolation, attestation.
• Ability to design monitoring and sensor systems for chiplet health.

What we offer

• Hybrid work environment with flexible schedule.
• Competitive compensation reflecting experience.
• Opportunities for professional growth within an innovative, inclusive team.