Digital Verification Intern

About the role

Monolithic Power Systems (MPS), a fast-growing semiconductor company worldwide known for integrated power semiconductors and systems power delivery architectures, is looking for a Digital Verification Engineer Intern in Barcelona. The intern supports validation, integration, simulation, debugging and verification of digital and mixed-signal ICs using industry-standard ASIC tools, with products that may cover power management, signal management and mixed-signal functions.

Key responsibilities

• Create digital verification environments with UVM and SystemVerilog.
• Write digital and mixed-signal testcases and assertions/checkers.
• Analyze and debug test results, code coverage and functional coverage.
• Support verification IPs and standard tests, environments and checkers.
• Help generate test plans based on design requirements and product datasheets.
• Work closely with senior digital design, digital verification and analog design engineers to develop system-level and behavioral models.
• Contribute to automation and scripting, and gate-level verification.

Required profile

• Bachelor's or MS in Electrical Engineering with emphasis on digital design or VLSI coursework.
• Ability to follow instructions and procedures according to design specifications.
• Good written and verbal communication skills and strong teamwork.

Required skills

• Basic knowledge of the ASIC development process and digital design techniques.
• Knowledge of standard DV languages (SystemVerilog, UVM) and behavioral/RTL coding.
• Plus: SCAN and other DFT techniques, power management applications, I2C/I3C/SPI/USB/PMBUS, and scripting languages such as TCL, Python and C/C++.