Senior DFT Design Engineer

About the role

A Senior DFT Engineer leads the end-to-end design, implementation, verification, validation and debugging of Digital and Mixed-Signal IC DFT architectures and solutions using leading-edge technologies and industry-standard ASIC tools. Products may cover power management, signal management and mixed-signal functions, including switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs.

Key responsibilities

• Develop and implement DFT architectures and techniques
• RTL design, debugging and verification
• Physical implementation, debugging and gate-level verification
• Generate high-quality test and debug patterns
• Perform STA and power analysis of DFT modes
• Support silicon bring-up, failure analysis, backtracking and diagnosis
• Define synthesis timing, I/O and DFT constraints, and analyse results and reports
• Define and debug LEC constraints and reports
• Generate and simulate ATPG
• Support analog, digital and mixed-signal AMS verification
• Work closely with Analog, Testing, Product and Digital teams
• Define test plans for analog and digital structural and functional testing

Required profile

• BSEE with 15 years of experience, or MSEE with 12 years as a DFT engineer
• Ability to work independently and collaborate with other teams
• Solid knowledge of the full ASIC development process
• Very good understanding of the backend flow: synthesis, P&R, DFT, power, LEC and STA

Required skills

• RTL Verilog or SystemVerilog coding
• Digital verification languages (SystemVerilog/UVM) and gate-level simulation
• Standard and advanced DFT techniques (ATPG, SCAN, IDDQ, delay fault, boundary scan, BIST, JTAG)
• ATE implementation, debugging and failure backtracking
• Trade-off between test quality and test time
• Plus: automotive standards, power management applications, I2C/I3C/SPI/USB/PMBUS, ARM/RISC-V, TCL/Python/C++, Cadence/Synopsius and Modus/Tetramax/TestSent/TestKompress/TestInsight